Today's semiconductor devices are continually being pushed to meet stricter demands in very large scale integrated (VSLI) circuits or integrated circuit (IC) chips. As these devices in VSLI circuits and systems or IC chips inundate the marketplace, consumers place higher demands on the devices. These demands include smaller, more compact devices with greater functionality. Semiconductor devices employ various circuitry in a chip to perform user specified functions. As is well known, the circuitry consists of various metallization lines, dielectric layers and other components interconnected throughout the entire chip. The metallization lines and other components are connected to transistors located at a lower level of the semiconductor device. The basic transistor has source and drain regions which are separated by a gate. By way of applying different voltages to the gate electrode, the transistor is either said to be ON or OFF.
Although there is a growing demand to scale transistor gate lengths to about 22 nm (i.e., 0.022 micron) and below for more demanding and compact digital circuit applications, such physical dimensions pose certain complexities. In particular, as transistors decrease in size the effects of process variability on the transistors continue to increase such that it is able to severely impact the functionality, yield and reliability of the transistors. For example, highly random effects that occur during processing of the transistors, such as random dopant fluctuations, oxide thickness variation and line-edge/width roughness, cause variability in the specific characteristics of each transistor. It is well known that variability increases with the decrease of transistor area. Thus, when the transistors are large, this variability only represents a small percentage of deviation in characteristics from transistor to transistor. However, as the transistors become smaller, that same level of variability becomes a larger and larger percentage of deviation to the point where the characteristics of one transistor can be substantially different than an identically designed second transistor. Thus, the process variability will only become a greater and greater concern as transistor dimensions are scaled down.
Another problem caused by the demand for smaller physical dimensions is the transistor off-state leakage current. Specifically, there is a need to cutoff leakage current of the order of zero in the off-state, and to produce low resistance or high device current in the on-state. However, for small gate length devices, even in the off-state, the space-charge region near the drain touches the source in a deeper place where the gate bias cannot control the potential, resulting in leakage current from the source to drain via the space-charge region. This is known as short-channel effect (SCE) which causes degradation in threshold voltage (Vth). As can be understood, for a transistor to work as a component of a digital circuit, the capability of switching OFF or the suppression of SCE is of high importance.
Yet another problem with the manufacturing of sub-22 nm transistors is the susceptibility to punch through. Punch through is generally understood to mean a case in which a dopant annealing process causes the source and drain depletion regions to come together. Since sub-22 nm transistors are pushing the limits on semiconductor manufacturing, transistor shorting or leakage due to punch through is a problem that needs to be addressed.